Method of reducing overetch during the formation of a semiconductor device
US6451678B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Nov 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.