Method of forming contact holes in a semiconductor device
US6451708B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming bit line contact holes simultaneously in the cell array region and the peripheral circuit region through a single-step photolithographic process using an etching stop phenomenon. Bit line contact holes are formed to expose a contact pad in the cell array region, to expose impurity diffusion region and to expose a gate electrode of a transistor in the peripheral region. Bit line contact holes are formed by a two-step etching process. The first etching step etches selectively insulating layers against a capping nitride of a transistor in the peripheral region, using a predefined photoresist pattern, thereby forming a first bit line contact hole to the contact pad in the cell array region, a bit line contact hole to the impurity region in the peripheral and an opening to the capping layer in the peripheral region. The second etching step etches the capping nitride to expose the gate electrode, using the same photoresist pattern, while no further etching occurs at the first and second bit line contact holes due to its relatively high aspect ratio. As a result, bit line contact holes are simultaneously formed both at the cell array region and peripheral circuit regio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.