High phase margin low power flip-flop
US6452433B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Aug 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved flip-flop circuit exhibits a higher phase margin than conventional flip-flop circuits without a substantial increase in operating power. The flip-flop circuit includes a master latch circuit operatively coupled to a slave latch circuit. The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave latch circuit relative to the sample-to-hold transition of the master latch circuit. The delay enables the flip-flop circuit to better tolerate clock/data timing alignment issues. In a first embodiment, the slave clock signal is delayed relative to the master clock signal. In a second embodiment, the master clock signal buffer is unbalanced such that its duty cycle is skewed to produce unequal sample and hold periods. In a third embodiment, the master latch circuit is unbalanced to create an unequal delay associated with the sampling and holding periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.