Multilayer inductor and method of manufacturing the same
US6452473B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2001 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | May 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F27/292
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A laminated inductor used for micro-miniaturized high frequency circuit includes insulating layers and conductive patterns alternately superimposed with each other, and the end of each conductive pattern is connected with each other to form a coil 3 in a laminated form. The starting end and terminal end of the coil 3 are connected with terminal electrodes 4, 5 at the opposed ends of the chip. The terminal electrodes 4, 5 are formed on, exception the side surface of the chip, the end surface and the lower surface of the chip or otherwise the end surface and upper and lower surfaces of the chip. This structure can minimize an adjacent portion between the coil 3 and the terminal electrodes 4, 5 so that a stray capacitance can be reduced. Thus, a high resonant frequency can be obtained for high frequency applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.