Jitter and load insensitive charge transfer
US6452531B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Aug 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for jitter and load insensitive charge transfer are disclosed. A quantity of charge is transferred to or from a load during a transfer interval, wherein the charge transferred is significantly insensitive to load characteristics and variations in the transfer interval. A succession of identical or different quantities of charge may be transferred to or from the load during successive transfer intervals. The charge transfer circuit may be employed in mixed switched/continuous-time circuit configurations, and in particular may be used as a unipolar or bipolar one-bit digital-to-analog converter to provide quantized feedback in a sigma-delta analog-to-digital converter circuit configuration. The charge transfer circuit avoids problems of integrating amplifier nonlinearity and input signal distortion in such sigma-delta analog-to-digital converter circuits, and facilitates monolithic fabrication of sigma-delta analog-to-digital converters using standard integrated circuit fabrication techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.