Clock generation for sampling analog video
US6452592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2001 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | May 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/008
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.