Power buss inhibit through data input/output lines
US6452770B1 · kind B1 · utility
0Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a CMOS integrated circuit card configuration operating upon a received data input stream and having a common power buss for the individual integrated circuits thereof, the invention comprises the connection of a power pin of all such individual integrated circuits directly to the power buss, except for the integrated circuit to which the data input stream is applied, wherein a diode of predetermined forward voltage drop is employed—having its anode connected to the power buss and its cathode connected to its associated power pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.