Method for baud-clock phase synchronization in a TDMA digital communications system and apparatus therefor
US6452948B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1998 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Jun 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0091
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A time division multiple access digital communications system (12) is provided. The system (12) has a base station (14) configured to generate a receive baud clock (86) and has a receiver (18) and a transmitter (20). The system also has a subscriber unit (16) configured to generate a transmit baud clock (50), and has a transmitter (28) and a receiver (26). The subscriber unit transmitter (28) is configured to transmit a reverse channel signal (54) that incorporates the transmit baud clock (50) as a component thereof. The base station receiver (18) is configured to receive the reverse channel signal (54) from the subscriber unit (16) and produce a phase-error signal (&mgr;′) in response to a phase difference between the transmit baud clock (50) and the receive baud clock (86). The base station transmitter (20) is configured to transmit the phase-error signal (&mgr;′) to the subscriber unit receiver (26). The subscriber unit transmitter (28) contains an interpolator (122) configured to adjust the phase of the transmit baud clock (50) in response to the phase-error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.