DDR DRAM data coherence scheme
US6453381B1 · kind B1 · utility
42Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Dec 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In this invention a double data rate (DDR) DRAM is read and written with data coherence. The data is in the form of a data burst either interleaved or sequential and of any length. The data is read from the DDR DRAM depending on whether the starting address is even or odd and taking into consideration CAS latency. Both edges of the clock are used to transfer data in and out of the DDR DRAM. To write data only the starting address of the data burst is used to maintain data coherence. Data coherence is assured by a write followed by a read of the same data to and from the same memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.