Memory interface device and memory address generation device
US6453394B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.