Apparatus and methods for controlling restart conditions of a faulted process
US6453430B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1438
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including a method and apparatus are provided for controlling fault conditions in a computer controlled device such as a data communications device. The invention can preferably be provided in a process restarter mechanism within an operation system. In operation, the process restarter system detects improper execution (i.e., detects a processing failure) of a set of instructions and initiates execution of the set of instructions in response to the operation of detecting. The system then repeats the operation of detecting and initiating according to a first restart sequence and then repeats the operation of detecting and initiating according to a second restart sequence. The second restart sequence initiates execution of the set of instructions in a different sequence than the first restart sequence. For example, the first restart sequence may perform process restarts quickly after failure detection, while the second restart sequence performs process restarts after longer and longer periods of time after failure detection. The quick restarts of the first restart sequence initially provide for maximum process uptime, and the delayed or progressively backed-off restarts allo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.