Method for cell modeling and timing verification of chip designs with voltage drop
US6453443B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2001 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Apr 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention a method is described to produce a whole chip timing verification that includes the effects of voltage variation on delay. This is done by creating a netlist, defining cell input and output (I/O) delay paths, and calculating the difference timing caused by differences in power supply voltage. The incremental I/O path delay is calculated by adding delay changes caused by all power pins. Whole chip timings are generated without consideration to voltage drops and then modified using the incremental path delay. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.