Semiconductor memory device having improved pattern of layers and compact dimensions
US6455899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A VDD wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a VSS wire, and a VDD wire are disposed extending in the Y-axis direction in the fourth conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.