Clock gate buffering circuit
US6456115B2 · kind B2 · utility
8Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Feb 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.