Phase error control for phase-locked loops
US6456165B1 · kind B1 · utility
14Cited by
23References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Aug 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0893
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) device includes phase error control for allowing quick transitions from a first operating point to a second operating point when the phase error exceeds a user-defined threshold. Phase error control is accomplished by adding an additional charge pump and accompanying user-settable circuitry to the PLL device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.