Test, reset and communications operations in an ARC fault circuit interrupter with optional memory and/or backup power
US6456471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S20/20
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An arc fault circuit interrupter system for use with an electrical circuit includes an arcing fault detector which monitors the electrical circuit and a controller which generates a trip signal in response to the detection of arcing faults. The controller may also generate one or more communication signals corresponding to information relating to the operation of the arcing fault circuit interrupter. The system may also include one or more of the following: a communication port which communicates to a user the information relating to operation of the arc fault circuit interrupter in response to the communication signals; a memory for retaining predetermined information related to the condition and operation of the arcing fault circuit interrupter, with or without a backup memory; and a combined self-test/reset switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.