System having memory devices operable in a common interface
US6456517B2 · kind B2 · utility
101Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
DRAM and SRAM devices have a NAND interface mode (pins whose address and data are identical to one another are commonly used), directly being coupled to buses (an address/data bus and a control bus) of a NAND-type flash memory device that is connected to a microprocessor. Upon such a common interface mode, a DRAM device, an SRAM device, a NAND-type flash memory device, and a NOR-type flash memory device have the identical interface mode, and are independently (or individually) controlled by only one memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.