Clock signal distribution and synchronization
US6456676B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Aug 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for clock signal distribution and synchronization are described. A base clock signal (e.g., system clock signal) is provided to multiple components of an electronic system. Two or more of the components include clock generation circuitry to generate component clock signals based on the base clock signal. The component clock signals are distributed to one or more other components within the electronic system. The component clock generation circuitry is allowed to synchronize to the base clock signal during a first predetermined period of time (e.g., system boot up). At the end of the first predetermined period of time, the base clock signal is blocked from the component clock generation circuitry for a second predetermined period of time. At the expiration of the second predetermined period of time, the component clock generation circuitry is allowed to re-synchronize with the base clock signal. Because multiple synchronizations are started at the same time, the resulting component clock signals are synchronized to the base clock signal and are in phase with each other (i.e., have a common phase).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.