Apparatus and method for a cache coherent shared memory multiprocessing system
US6457087B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.