Structure and method for automatic configuration for SCSI Synchronous data transfers
US6457090B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel SCSI host adapter integrated circuit includes a memory containing a table having a plurality of entries. Each entry in the plurality of entries is a parameter used in a data transfer over a SCSI bus to a target device. A target identification register stores a pointer to the table. A SCSI transfer parameter register is coupled to the memory. An entry in the table pointed to by the value stored in the target identification register is loaded into the SCSI transfer parameter register. Another SCSI transfer parameter register also is coupled to the memory so that another entry stored in the table is loaded into the another SCSI transfer parameter register. A decoder circuit connected to the a SCSI transfer parameter register has a set SCSI attention signal output line, an enable SCSI asynchronous transfer output line, and a reset SCSI attention signal output line. When a value in the SCSI transfer register indicates an asynchronous data transfer, the decoder circuit generates an active signal on the enable SCSI asynchronous transfer output line. When a value in the SCSI transfer register indicates an asynchronous data transfer, and a value in the another SCSI transfer regis…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.