Shared memory control system and shared memory control method
US6457106B1 · kind B1 · utility
6Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Jul 22, 1998 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jul 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a current shared memory cycle, the memory access band value of each bus master is calculated at any time and discriminated to determine the next memory cycle control before completion of the current shared memory cycle, so that the minimum memory access band value required by each bus master is maintained with the result that the shared memory can be efficiently utilized. Thus, there is provided a shared memory control apparatus and a shared memory control method, capable of realizing a memory control of an excellent efficiency by maintaining the memory access band width per unit time, required by the master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.