System and method for managing a plurality of processor performance states
US6457135B1 · kind B1 · utility
125Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Aug 10, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system having a processor capable of operating at a plurality of performance states, wherein each of the plurality of performance states has an expected processing performance, a system and method is described for switching between the plurality of performance states. A determination is made that a performance state change is needed. The system waits for the processor to enter a quiescent state and, when the processor enters the quiescent state, places the processor in the new performance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.