System and method for crash handling on redundant systems
US6457138B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Apr 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to providing processor redundancy in a system such as a router. According to an embodiment of the present invention, when a primary processor is about to crash in a system having two or more processors, the imminent crash is identified prior to the occurrence of the actual crash. The primary processor sends a message to the secondary processor to indicate that it is crashing. The primary also sets a timer to determine a period of time to wait prior to crashing. When the secondary processor receives the message from the primary processor, the secondary processor becomes the new primary processor. The new primary processor then sends an acknowledgement to the old primary processor. The old primary processor crashes and reboots as the new secondary processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.