Detecting address faults in an ECC-protected memory
US6457154B1 · kind B1 · utility
36Cited by
9References
40Claims
0Family size
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Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Uncorrectable errors are detected during the transmission of a data word according to an error correction code. Then, any address faults are identified from among the detected uncorrectable errors. In addition, address faults as well as uncorrectable memory data failures are detected from among the detected uncorrectable errors. Furthermore, address parity bits are not required to be stored to memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.