Method and system for constructing and manipulating a physical integrated circuit layout of a multiple-gate semiconductor device
US6457163B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method and system for the automated construction and manipulation of a physical integrated circuit layout of a multiple-gate semiconductor device, wherein the layout is comprised of a plurality of gate glue-blocks interconnected by a plurality of active-layer glue-blocks, working shapes of the gate glue-blocks are initially created according to user-defined gate glue-block parameters. Thereafter, working shapes of the active-layer glue-blocks are created in accordance with the working shapes of adjacent ones of the gate glue-blocks, in which the distances among the working shapes exceed minimum geometrical distances as defined by relevant design rules of an applied fabrication technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.