Self-aligned interconnect and method for producing same
US6457811B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB41J2202/20
- WIPO fieldTextile and paper machines
- WIPO sectorMechanical engineering
Abstract
A self-aligned interconnect significantly reduces manufacturing costs and provides important advantages in a number of specific applications begins with a single crystal substrate. The substrate is machined to accept microelectronic chips at various locations (openings) along the substrate. Corresponding chips are constructed to precisely fit the openings in the crystal substrate. To ensure precision fit, both the substrate and the chip are etched along the same crystal plane. As a result, the chips can be placed in the openings in the substrate with perfect or nearly perfect alignment in the x and y directions without expensive alignment tools. In effect, the chips and the substrate are self aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.