Patent · US Expired

Divide by 15 clock circuit

US6459310B1 · kind B1 · utility

8Cited by

2References

22Claims

0Family size

Assignee

Nortel Networks Limited · CA

Inventors

Sandy Thomson · Ottawa, CA
Paul MacDonald · Ottawa, CA

Key dates

Filing date	Jul 6, 2001
Grant date	Oct 1, 2002
Priority date	—
Expiry date	Jul 6, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/18
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock divider circuit for generating an output clock signal derived from an input clock signal with the output clock signal having a selected frequency and duty cycle. The clock divider circuit comprises a linear shift register with a feedback loop. Data is shifted through the stages of the linear shift register in response to the input clock signal being applied at a clock input port. The output clock signal is derived from the data outputs on selected stages in the linear shift register. In one aspect, the clock divider circuit divides a 667 MHz input clock signal to generate a 44 MHz output clock signal having a 50% duty cycle. In another aspect, the clock divider circuit divides a 669 MHz input clock signal to generate a 45 MHz output clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.