Impedance matching circuit for semiconductor memory device
US6459320B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Apr 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An importance matching circuit for a semiconductor memory device includes an impedance detector for generating a voltage divided by a medium resistance value between a maximum resistance value and a minimum resistance value and an external resistance during a predetermined cycle as a first comparison voltage, and for generating a voltage divided by a resistance value varied in response to a counting output signal and the external resistance after the predetermined cycle as the first comparison voltage; a first comparator for comparing the first comparison voltage with a reference voltage to generate a first comparing output signal; a second comparator for comparing the first comparison voltage with the reference voltage to generate a second comparing output signal; a counter for generating the counting output signal in response to the first comparing output signal; and a plurality of output drivers for establishing an initial resistance value in each of the output drivers in response to the second comparing output signal and for adjusting a resistance value in each of the output drivers in response to the counting output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.