Split-bank architecture for high performance SDRAMs
US6459647B1 · kind B1 · utility
30Cited by
4References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Feb 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the memory bank segments are proximally positioned relative to associated I/Os. In this way, the delay times from each of the memory bank segments to their respective I/Os are substantially equal to each other. In addition, the proximal positioning of the memory banks results in reduced signal delays due to reduced signal paths from each bank segment and respective I/O.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.