Method and apparatus for asynchronously controlling a DRAM array in a SRAM environment
US6459650B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for asynchronously controlling a DRAM array in an SRAM environment is described. In on embodiment, this is a method of arbitrating between a refresh request and an access request. Furthermore, the access request may be either a read or a write request. Moreover, the request may be generated by a refresh control circuit within a circuit implementing the asynchronous control method. In an alternate embodiment, this is an apparatus. The apparatus includes an arbitration circuit block which may receive a refresh request and an access request. Furthermore, the access request may come as a read request or a write request, which may be implemented as separate signals. Moreover, the apparatus may include a refresh circuit block which may generate refresh control signals and the refresh request signal for the arbitration circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.