Multi-shifting shift register
US6459751B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | May 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector. The input end of the flip-flop of each of the register units is connected to the output of the selector of a preceding one of the register units. A jth one of the address signal inputs of the selector of each of the registers units is connected to the output end of the flip-flop of a (j−1)th preceding one…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.