Low cost data streaming mechanism
US6460108B1 · kind B1 · utility
49Cited by
24References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1999 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.