Dynamic memory clock control system and method
US6460125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory clock control system and method facilitates power reduction on a dynamic basis by detecting memory access request loading from a number of memory access devices, such as video and graphics engines. Based on the detected memory access requirements, the system and method adaptively varies a memory clock frequency in response to determining the desired memory usage at a given point in time. The memory clock is varied based on the priority of a given memory access engine, such that the clock is kept or increased to a higher rate for high priority engines such as real-time processing engines to facilitate high performance video capture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.