Method for designing a processor core in which a cell configured at either one or zero is provided for each bit of the configuration registers of the processor core
US6460171B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero. The processor core is programmed by instantiating the non-programmed core, instantiating a programming block having a cell configured at either one or zero for each bit of the configuration registers, and superimposing each of the configured cells of the programming clock on the location of a corresponding vacant …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.