Process for making active interposer for high performance packaging applications
US6461895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jun 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4623
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) package process is provided that includes forming a first via hole in a first substrate. Patterning signal lines on a first surface and a second surface of the first substrate. Attaching a second substrate to the first surface of the first substrate. Electronically connecting a portion of the signal lines of the first substrate and the second substrate. Attaching an electrical element to the first surface of the first substrate. Forming a via hole in a third substrate. Introducing conductive material over a first surface and a second surface of the third substrate. Forming a second circuit pattern on the first surface and the second surface of the third substrate. Additionally, attaching the third substrate to the first substrate with a second layer of adhesive. In an alternative embodiment, a process includes forming a via hole in a first substrate. Introducing conductive material over a first surface and a second of the first substrate, wherein the introducing conductive material over the first surface and the second surface of the first substrate fills the via hole to form a via and a through hole. Forming a first circuit pattern on the first surface a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.