System and method for alternating standby mode
US6462437B1 · kind B1 · utility
23Cited by
13References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for reducing the level of power consumption in an electronic device when the electronic device is operating in a standby mode or low-power mode. The level of power consumption is reduced by alternately shutting off standby power and turning on standby power to the electronic device. A standby cycle timer circuit is provided for automatically controlling the supply of standby power to the electronic device during standby mode. The standby cycle timer circuit becomes inactive when the electronic device resumes normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.