Dynamic biasing techniques for low power pipeline analog to digital converters
US6462695B1 · kind B1 · utility
12Cited by
9References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuitry for implementing low-power analog-to-digital converters. More particularly, embodiments of the present invention provide an amplifier circuit for pipeline ADCs having multiple stages, some in sample mode, some in hold mode. The stages include residue amplifiers which include a pre-amp and a current source. The current source is turned off during the sample mode. Some embodiments include a second current source that provides a bleeder current during the sample phase so that the pre-amp remains in steady state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.