Data storage device having virtual columns and addressing layers
US6462977B2 · kind B2 · utility
18Cited by
44References
60Claims
0Family size
Inventor
Key dates
| Filing date | May 9, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | May 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is disclosed. The memory device includes, in some embodiments, a plurality of virtual columns that may be addressed by applying an address to a plurality of address layers of the memory device. The virtual columns include addressable elements coupled to the address layers. The addressable elements allow for a data storage element associated with the virtual columns to be accessed for read/write operations when each addressable element receives a particular signal as an input from the address layer to which it is coupled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.