Direct-comparison reading circuit for a nonvolatile memory array
US6462987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Aug 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and at least one bit line, includes at least one array line, selectively connectable to the bit line, and a reference line; a precharging circuit for precharging the array line and reference line at a preset precharging potential; at least one comparator having a first terminal connected to the array line, and a second terminal connected to the reference line; and an equalization circuit for equalizing the potentials of the array line and reference line in the precharging step. In addition, the reading circuit includes an equalization line distinct from the reference line; and controlled switches for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line from the array line and from the reference line at the end of the precharging step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.