Low latency input-output interface
US6463483B1 · kind B1 · utility
12Cited by
4References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.