Apparatus and method for testing master logic units within a data processing apparatus
US6463488B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jun 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a data processing apparatus and method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units for accessing a bus in order to initiate processing requests, and a test controller for testing logic units of the data processing apparatus. Further, an arbiter is provided for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller. In a normal test mode, the test controller has a higher priority than any of the master logic units to be tested. However, in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter is arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.