Superscalar processor and method for incrementally issuing store instructions
US6463524B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A superscalar processor and method are disclosed for efficiently executing a store instruction. The store instruction is stored in an issue queue within the processor. A first part of the store instruction is issued from the issue queue to a first one of different execution units in response to a first operand becoming available. A second part of the store instruction is issued from the issue queue to a second one of the different execution units in response to a second operand becoming available. The store instruction is completed in response to executing the first part of the store instruction by the first one of the execution units and the second part of the store instruction by the second one of the execution units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.