Method and apparatus for monitoring a microprocessor
US6463546B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Feb 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0754
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A watchdog circuit for a microprocessor which has a reset input and a control output, which output, when operation is normal, periodically delivers, under program control, a signal (P0B2) of predefined duration (t1); and having a capacitor (32) that can be charged via a charging circuit; having a discharging circuit (40, 42), controlled by the control output, for said capacitor (32), for periodic discharge thereof during the predefined duration (t1); the charging circuit and discharging circuit being adapted to the program sequence of the microprocessor such that when the microprocessor is operating normally, charging of the capacitor via the charging circuit corresponds respectively to discharge thereof via the discharging circuit; so that the voltage at said capacitor rises and falls within a predefined voltage range; and having an apparatus (30), for monitoring the charge state of said capacitor (32), which, in the presence of a charge state thereof that does not occur in normal operation, effects a reset operation in the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.