Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits
US6463560B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jun 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.