Full-chip extraction of interconnect parasitic data
US6463571B1 · kind B1 · utility
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Key dates
| Filing date | Mar 14, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jun 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In this method for hierarchical extraction of interconnect parasitic data for integrated circuits, a representation of coupled interconnects and polygon data copied from an upper level to a lower level is simplified so that the coupled interconnects and the polygon data are considered to be ground wires. This method also features instance-specific management of hardmac data from copied hardmac views to create SPEF files using both chip level and macro level back-annotation in a hierarchical representation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.