Recessed silicon oxidation for devices such as a CMOS SOI ICs
US6465324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided to form a LOCOS isolation in a CMOS SOI device. The SOI has a top silicon layer, a bottom silicon layer, and an insulation layer between the top and bottom silicon layers. An oxide layer is formed over the top silicon layer, and an LPCVD layer is deposited over the oxide layer. A photoresist is provided over the LPCVD layer that exposes a localized area of the LPCVD layer. The LPCVD layer and the oxide layer are etched away through the localized area to expose the top silicon layer. The silicon in the top silicon layer is etched so as to form a recess in the top silicon layer. The photoresist is removed and an isolation oxide is grown over the silicon in the recess so that the silicon in the recess is fully oxidized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.