Multiplexers for efficient PLD logic blocks
US6466051B1 · kind B1 · utility
19Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Feb 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to (i) implement user defined programmable logic and (ii) generate an output in response to a first input and a second input. The second circuit may be configured to generate the second input in response to the output, a third input, and a fourth input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.