Programmable architecture for visualizing sampled and geometry data
US6466227B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Sep 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable visualization apparatus processes graphical data. The apparatus includes a central processing unit for executing a visualization application and a scheduler. A third level of memory is connected to the central processing unit. The third level of memory stores the graphical data. The graphical data is partitioned into a plurality of blocks. A second level of memory is connected to the central processing unit by a system bus. The second level of memory stores a sub-set of the plurality of blocks. A first level of memory is connected to the second level of memory by a memory bus. The scheduler stores an ordered list of blocks in the first level memory. A processor element is connected to the first level of memory by a processor bus. A dispatcher is connected to the first, the second, and the third memories and the processor element. The dispatcher transfers blocks from the third, to the second, and from the second to the third level memories according to the order of the list of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.