Method and circuit for reducing voltage level variation in a bias voltage in a power converter
US6466461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2002 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Feb 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/33569
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Circuit and method for reducing voltage level variation in a bias voltage generated in a power converter device are provided. The method allows providing a first voltage source configured to supply a first voltage during one respective mode of operation of the power converter, wherein the level of the voltage supplied by the first voltage source is directly proportional to variation in an input voltage of the converter device. The method further allows providing a second voltage source configured to supply a second voltage during another respective mode of operation of the power converter, wherein the level of the voltage supplied by the second voltage source has a generally inverse proportional relationship relative to variation in the input voltage of the converter device. At least one circuit parameter is selected in the voltage sources to adjust the respective levels of the first and second voltages. The first and second voltages are combined with one another to generate a combined voltage that comprises the bias voltage in the power converter device, the combined voltage resulting in a bias voltage level being relatively impervious to variation in the input voltage of the conv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.