Method and apparatus for increasing signal to sneak ratio in polarizable cross-point matrix memory arrays
US6466473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Mar 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.